1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device in which read information is detected by amplifying the potential difference appearing in each bit line pair.
2. Description of the Background Art
FIG. 9 is a block diagram showing the whole structure of a conventional general dynamic random access memory (hereinafter referred to as DRAM). In the diagram, signal input terminals 2, 3 and 4 are provided on the periphery of a semiconductor chip 1. A row address signal RA and a column address signal CA are supplied as inputs from signal input terminal 2 in a time sharing manner. A row address strobe signal /RAS is supplied as an input from signal input terminal 3. A column address strobe signal /CAS is supplied as an input from signal input terminal 4. A row address buffer 5 fetches the row address signal, supplied as an input, in synchronism with the row address strobe signal /RAS, and holds the row address signal. A column address buffer 6 fetches the column address signal, supplied as an input, in synchronism with the column address strobe signal /CAS and holds the column address signal. The row address signal RA0 - RAn held in row address buffer 5 is supplied to a row address decoder RD. The row decoder RD decodes the supplied row address signal RA0 - RAn and selectively drive a word line in a memory cell array MCA. The least significant bit signal RA0 of the row address signal RA0 - RAn is supplied to a selector circuit 7. The selector circuit 7 is responsive to the least significant bit signal RA0 and selectively drives either of the dummy word lines DWLe and DWLo. These dummy word lines DWLe and DWLo are connected to the memory cell array MCA. A plurality of bit line pairs BL, /BL are provided, crossing a plurality of word lines, in the memory cell array MCA. A sense amplifier SA, for example, of the structure as shown in FIG. 11 is provided to each bit line pair. Moreover, each bit line pair BL, /BL is connected, through transfer gates Q1, Q2 each implemented with a N channel MOS transistor, to a data input/output line pair IO, /IO. On the other hand, the column address signal CA0 - CAn held in column address buffer 6 are supplied to a column decoder CD. The column decoder CD decodes the supplied column address signal CA0 - CAn and selectively turns on a transfer gate pair of the plurality of transfer gate paifs Q1, Q2. The data input/output line pair IO, /IO is connected to an IO buffer 8. The IO buffer 8 is connected to a data input/output terminal 9 provided on the periphery of semiconductor chip 1. More specifically, IO buffer 8 performs inputting/outputting of data between data input/output terminal 9 and the data input/output line pair IO, /IO.
Moreover, the row address strobe signal /RAS and the column address strobe signal /CAS which are input to signal input terminals 3, 4 are supplied to a clock generating circuit 10. The clock generating circuit 10 is responsive to the supplied row address strobe signal /RAS and column address strobe signal /CAS to output clock signals BLPR, .phi.s and /.phi.s. The clock signal BLPR is supplied to the memory cell array MCA. The clock signals .phi.s, /.phi.s are supplied to the gates of transistors 11, 12 which cause the sense amplifiers SA to change in the active state.
FIG. 10 is a circuit diagram showing in more detail the memory cell array and its peripheral circuits extracted from the conventional DRAM shown in FIG. 9. In FIG. 10, a plurality of bit line pairs BL, /BL are arranged, crossing a plurality of word lines WL in the memory cell array MCA. Memory cells MC are connected to the crossings of each bit line pair BL, /BL and each word line WL. Each memory cell MC includes a transfer gate TG implemented with a N channel MOS transistor and a memory cell capacitor Cs in which information of a high level or "H", or low level or "L" is stored as a charge. A voltage Vcp is applied from a common power source (not shown), through a cell plate line CPL, to one electrode (cell plate electrode) of the memory cell capacitor Cs of each memory cell MC. Moreover, dummy word lines DWL0, DWL1 are arranged, crossing the bit line pairs BL, /BL. A dummy cell DC0 is provided at the crossing of the dummy word line DWL0 and each bit line BL, and a dummy cell DC1 is provided at the crossing of the dummy word line DWL1 and each bit line /BL. Each of the dummy cells DC0 and DC1 has the same structure as that of the memory cells MC and holds the intermediate voltage between the supply voltage Vcc and the ground voltage.
Furthermore, a sense amplifier SA is connected to each bit line pair BL, /BL. The plurality of word lines WL are connected to a row decoder RD. The dummy word lines DWL0, DWL1 are connected to a selector circuit 7. The bit line pairs BL, /BL are connected, through the transfer gates Q1, Q2 each implemented with a N channel MOS transistor, to the data input/output line pair IO, /IO. The gates of the transfer gates Q1, Q2 are connected to the column decoder CD.
Furthermore, each bit line BL is connected, through a transfer gate T.sub.EQ 1 implemented with a N channel MOS transistor, to a precharge line 13. Each bit line /BL is connected, through a transfer gate T.sub.EQ 2 implemented with a N channel MOS transistor, to a precharge line 13. A precharge voltage of Vcc/2 is applied to precharge line 13. A clock signal BLPR is applied from the clock generating circuit 10 shown in FIG. 9 to the gate of each of the transfer gates T.sub.EQ 1, T.sub.EQ 2.
When data is read, a word line WL is selected by the row decoder RD, and the potential of the word line WL is raised to "H". This causes the data in the memory cell MC connected to the word line WL to be read onto the bit line BL or /BL. For example, when the data is read onto the bit line BL, the potential of the dummy word line DWL1 is raised to "H", and the potential in the dummy cell DCI is read onto the bit line /BL. This causes the potential of the bit line /BL to become a reference potential Vref. On the other hand, the potential of the bit line BL becomes slightly higher or lower than the reference potential Vref according to the read out data. Then, the potential difference between the bit lines BL and /BL is amplified by a sense amplifier SA. Any one pair of transfer gates Q1, Q2 are turned on by a column decoder CD, and the data on the bit line pair BL, /BL connected to the pair of transfer gates Q1, Q2 is read onto the data input/output line pair IO, /IO.
Now, the potential appearing on each bit line pair BL, /BL during the read operation is considered. Let the capacitance value of the memory cell capacitor Cs of the memory cell MC be Cs. The charge stored in the memory cell MC becomes Cs.multidot.(Vcc-Vcp) when data of "H" is stored (when Vcc is written) and becomes Cs.multidot.(-Vcp) when data of "L" is stored (when 0V is written). Moreover, a charge represented by Cs.multidot.((Vcc/2)-Vcp) is stored in the dummy cells DC0 and DC1 in which a voltage of Vcc/2 is written. If the bit line pair BL, /BL is precharged to a potential of Vcc/2 before the read operation, the charge on the bit lines BL, /BL becomes C.sub.B .multidot.(Vcc/2), where C.sub.B is stray capacitance of the bit line BL or /BL.
FIG. 12 is a diagram showing the structure of the part related to a bit line pair extracted from the DRAM shown in FIG. 10. In FIG. 12, for example, in the case where data is read from the memory cell MC to the bit line BL, and the potential from the dummy cell DC1 is read onto the bit line /BL, the potential VBL of the bit line BL and the potential VBL, of the bit line /BL are evaluated from the following equations (1) and (2). ##EQU1##
Further, in the above equation (1), the sign+of the sign .+-. indicates the case when Vcc is written, and the sign - of the sign .+-. indicates the case when 0V is written. ##EQU2##
From the above equations (1) and (2), the potential difference .DELTA.VBL (=VBL-VBL') between the bit lines BL and /BL is as shown in the following equation (3). EQU .DELTA.VBL=(Cs.multidot.Vcc)/{2 (C.sub.B +Cs)} (3)
Now, in accordance with rapid progress in technology in recent years, there is a tendency for semiconductor memory devices to be increasingly miniaturized. A higher degree of integration of semiconductor integrated circuit devices makes the area of a memory cell MC inevitably become smaller, and the capacitance value of a memory cell capacitor Cs is reduced. However, as a conventional DRAM was constructed as described above, if a higher degree of integration reduces the capacitance value of a memory cell capacitor Cs, the read potential difference becomes smaller. As a result, a problem has arisen that the incidence of a soft error increases. Another problem has also arisen that it causes reduction of the margin of reading and malfunction of a sense amplifier.
Therefore, a semiconductor memory device has been conventionally proposed which can make larger the read potential difference between a bit line pair without making larger a memory cell capacitor. Such prior art is described in the following.
FIG. 13 is a circuit diagram showing the structure of a part of the memory cell array in the semiconductor memory device shown in Patent Laying-Open No. Sho 60-164989. In the diagram, each memory cell MC belonging to the bit line /BL has the cell plate electrode of respective memory capacitor Cs connected, through a transistor 21, to the bit line /BL. Each memory cell MC belonging to the bit line /BL has the cell plate electrode of respective memory cell capacitor Cs connected, through a transistor 22 to the bit line BL. The gate of each of the transistors 21, 22 is connected to the corresponding one of the word lines, respectively.
FIG. 14 is a circuit diagram showing the structure of a part of the memory cell array in the semiconductor memory device shown in Patent Laying-Open No. Sho 60-239993. In the diagram, each memory cell MC belonging to the bit line BL has the cell plate electrode of respective memory cell capacitor Cs connected to the bit line /BL. Each memory cell MC belonging to the bit line /BL has the cell plate electrode of respective memory cell capacitor Cs connected to the bit line BL.
In the semiconductor memory devices shown in FIGS. 13 and 14, the one and the other electrodes of the memory cell capacitor Cs of each memory cell MC are connected to the one and the other bit lines of the corresponding bit line pair, respectively. As a result, when data is read from the memory cell MC, the potentials of the bit lines BL and /BL change in the directions opposite to each other, and the read potential difference increases. Therefore, there is an advantage that the incidence of soft error can be decreased, the margin of reading is increased and a semiconductor memory device with less malfunction is obtained.
On the contrary, the semiconductor memory devices shown in FIGS. 13 and 14 has a problem as described in the following.
First, since in the semiconductor memory device shown in FIG. 13, each memory cell MC includes three elements, there has been a problem that the area of the memory cell becomes large and it prevents a higher degree of integration. Besides, since the semiconductor memory device shown in FIG. 13 has the output (having a large potential difference) of a sense amplifier (not shown) directly applied to the memory cell capacitor Cs when data is rewritten in a memory cell MC after reading data from the memory cell MC has been ended, there has been a problem that a high electric field is applied to the memory cell capacitor Cs so that the dielectric film of the memory cell capacitor Cs may be broken. To solve the latter problem, it is considered to increase the thickness of the dielectric film of the memory cell capacitor Cs; however, it causes the capacitance value of the memory cell capacitor Cs to become small and the stored charge amount in the memory cell capacitor to be reduced. It is also considered to decrease the voltage applied to the memory cell capacitor Cs by some means; however, it makes control complicated.
On the other hand, in the semiconductor memory device shown in FIG. 14, the output of the sense amplifier (not shown) is also directly applied to the memory cell capacitor Cs, so that a problem has arisen that a high electric field is applied to the memory cell capacitor Cs in the same manner as in the semiconductor memory device shown in FIG. 13.